Robotics · ROSCon · ROS · AMD · SoC

Hardware Acceleration in Robotics #84

By Acceleration Robotics · Nov 3, 2023

News

September 2023 robotics investments total $1.84 billion

Source: Robotics Business Review, October 31, 2023 [1]
September 2023 robotics funding totaled $1.84 billion, the result of 50 investments. Total funding for the months of January 2023 through September 2023 equals approximately $10.7 billion.

Thoughts on ROSCon 2023

Source: Weekly Robotics Newsletter, October 29, 2023 [2]
This post summarizes some of the highlights of the event.

Reflections on ROS in Asia

Source: LinkedIn, October 16, 2023 [3]
The International Federation of Robotics reported that a whopping 73% of “all newly deployed robots” last year were installed in Asia.

AMD sees profit surge as it banks on AI chips

Source: Silicon Republic, November 1, 2023 [4]
The company predicts that its MI300 AI accelerator chip will be the fastest product to reach $1bn in sales ‘in AMD history’.

System-on-Chip integration complexity and hardware/Software contracts

Source: Semiconductor Engineering, October 26, 2023 [5]
Control and status register mismanagement can lead to expensive oversights.

Bringing tiny Chiplets to embedded socs

Source: EE Times, October 27, 2023 [6]
ZeroASIC has developed a technology platform to bring chiplets to embedded system design, as a time-efficient alternative to designing and manufacturing custom application-specific ICs (ASICs).

What will that chip cost?

Source: Semiconductor Engineering, November 1, 2023 [7]
Establishing the true cost to develop an advanced chip is complicated, but headline numbers appear to be significantly inflated.

Decoding the functions of a processor

Source: The New Indian Express, November 1, 2023 [8]
These tiny chips are responsible for executing instructions, performing complex calculations, and enabling seamless functions on computers and smartphones.

Papers

Enabling HW-based task scheduling in large Multicore architectures

Source: IEEE Xplore, October 12, 2023 [9]
Dynamic Task Scheduling is a programming model that simplifies parallel program development, reducing scheduling overheads. Traditional SW-only systems have limited capacity for core count and task granularity. This study presents an FPGA-proven, Linux-capable 30-core RISC-V system with hardware accelerated Task Scheduling, demonstrating its competitive performance at high core counts. The architecture includes hardware and software optimizations, making it more scalable than previous solutions.

GateSeeder: Near-memory CPU-FPGA acceleration of short and long read mapping

Source: arXiv, September 29, 2023 [10]
Read mapping is a costly and time-consuming process in genomics analyses, primarily affecting Index Querying, Seed Chaining, and Sequence Alignment. This work aims to improve these steps by utilizing new algorithms and hardware devices. GateSeeder, the first CPU-FPGA-based near-memory acceleration for both short and long read mapping, uses modern FPGAs' near-memory computation capability and a lightweight algorithm for finding potential matching segment pairs. Experimental results show GateSeeder outperforms Minimap2 without sequence alignment.

Previous Hardware Acceleration in Robotics Newsletters

Past ROS 2 Hardware Acceleration Working Group meetings

  1. Kara, D. (2023, October 31). September 2023 robotics investments total $1.84 billion. Robotics Business Review. https://www.roboticsbusinessreview.com/rbr-investment/september-2023-robotics-investments-total-1-84-billion/ ↩︎

  2. Sadowski, M. (2023, October 29). Thoughts on ROSCon 2023. Weekly Robotics Newsletter . https://www.weeklyrobotics.com/articles/2023_10_29_roscon_2023/ ↩︎

  3. Festo, M. (2023, October 16). Reflections on ROS in Asia. LinkedIn. https://www.linkedin.com/pulse/reflections-ros-asia-matthew-festo-jvmgc/ ↩︎

  4. Gowran, L. (2023, November 1). AMD sees profit surge as it banks on AI chips. Silicon Republic. https://www.siliconrepublic.com/business/amd-earnings-profit-ai-accelerator-chips ↩︎

  5. Schirrmeister, F. (2023, October 26). System-on-Chip integration complexity and hardware/Software contracts. Semiconductor Engineering. https://semiengineering.com/system-on-chip-integration-complexity-and-hardware-software-contracts/ ↩︎

  6. Ward-Foxton, S. (2023, October 27). Bringing tiny Chiplets to embedded socs. EE Times. https://www.eetimes.com/bringing-tiny-chiplets-to-embedded-socs/ ↩︎

  7. Bailey, B. (2023, November 1). What will that chip cost? Semiconductor Engineering. https://semiengineering.com/what-will-that-chip-cost/ ↩︎

  8. Raj, A. (2023, November 1). Decoding the functions of a processor. The New Indian Express. https://www.newindianexpress.com/xplore/2023/nov/01/decoding-the-functions-of-a-processor-2628957.html ↩︎

  9. Morais, L., Álvarez, C., Jiménez-González, D., Miguel de Haro, J., Araujo, G., Frank, M., Goldman, A., & Martorell, X. (2023, October 12). Enabling HW-based task scheduling in large Multicore architectures. IEEE Xplore. https://ieeexplore.ieee.org/abstract/document/10284544 ↩︎

  10. Eudine, J., Alser, M., Singh, G., Alkan, C., & Mutlu, O. (2023, September 29). GateSeeder: Near-memory CPU-FPGA acceleration of short and long read mapping. arXiv. https://arxiv.org/pdf/2309.17063.pdf ↩︎

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